Formal Verification of Simulink/Stateflow Diagrams: A Deductive Approach

Formal Verification of Simulink/Stateflow Diagrams: A Deductive Approach

Springer | Engineering | December 6. 2016 | ISBN-10: 3319470140 | 258 Pages | PDF | 4.17 MB

Authors: Zhan, Naijun, Wang, Shuling, Zhao, Hengjun
Provides development of the method, from theories to implementations, and then to applications
Covers a broad range of topics, both theoretical and practical, including hybrid systems, deductive verification, Duration Calculus, dynamical systems, computer algebra, Simulink/Stateflow, Isabelle theorem prover, etc.
Uses "hands-on" presentation of implementations and case studies from real industrial systems

This book presents a state-of-the-art technique for formal verification of continuous-time Simulink/Stateflow diagrams, featuring an expressive hybrid system modelling language, a powerful specification logic and deduction-based verification approach, and some impressive, realistic case studies. Readers will learn the HCSP/HHL-based deductive method and the use of corresponding tools for formal verification of Simulink/Stateflow diagrams. They will also gain some basic ideas about fundamental elements of formal methods such as formal syntax and semantics, and especially the common techniques applied in formal modelling and verification of hybrid systems. By investigating the successful case studies, readers will realize how to apply the pure theory and techniques to real applications, and hopefully will be inspired to start to use the proposed approach, or even develop their own formal methods in their future work.

Number of Pages
XV, 258
Number of Illustrations and Tables
14 b/w illustrations, 60 illustrations in colour
Topics
Circuits and Systems
Processor Architectures
Electronic Circuits and Devices

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