High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

English | ISBN: 9811010722 | 2017 | 220 Pages | PDF, EPUB | 19 MB

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

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