Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

2006 | pages: 180 | ISBN: 140204139X | PDF | 3,2 mb

The evolution of the CMOS technology brings many challenges to analog designers. The scaling-down of the transistor feature size has a big impact on analog circuit de-sign, because it considerably degrades the performance of an analog circuit. As an interface between the analog circuit and the digital circuit, the ADC is moving into nanometer CMOS technologies due to the advantages for the digital circuit. Con-sequently, the reduced supply voltage and the degraded device characteristic are in-evitable problems in ADC design. Many efforts have been devoted to cope with these problems to make an ADC design in nanometer CMOS technologies. In this text, the circuit level approach and the system level approach are presented for low-power low-voltage-ADC design in nanometer CMOS technologies.



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