Modeling of Electrical Overstress in Integrated Circuits



Springer; 1995 edition | October 4, 2013 | English | ISBN: 1461362059 | 148 pages | PDF | 11 MB

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs).

These reliability concerns are becoming more serious with the downward scaling of device feature sizes.

Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.

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