Static Timing Analysis for Nanometer Designs

Static Timing Analysis for Nanometer Designs

English | Apr. 17, 2009 | ISBN: 0387938192 | 1174 Pages | PDF | 15 MB

iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication.


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