Wafer Level 3-D ICs Process Technology

Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif, "Wafer Level 3-D ICs Process Technology"
Spri/nger | 2008 | ISBN: 0387765328 | 410 pages | File type: PDF | 11,1 mb

This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging.

This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

Download links:




[Fast Download] Wafer Level 3-D ICs Process Technology

Related eBooks:
Analysis and Design of Quadrature Oscillators
California 2014 Journeyman Electrician Study Guide
Design Recipes for FPGAs: Using Verilog and VHDL
Mobile Crowd Sensing: Incentive Mechanism Design
Nanoelectronics, Circuits and Communication Systems: Proceeding of NCCS 2017
Multi-terminal High-voltage Converter
Mini-Grids for Rural Electrification of Developing Countries: Analysis and Case Studies from South A
Anwendungsorientierte Mikroprozessoren: Mikrocontroller und Digitale Signalprozessoren
Instrumentation And Control
Advanced Electrical and Electronics Engineering, Volume 2
Testing of Interposer-Based 2.5D Integrated Circuits
Essential DC/DC Converters
Copyright Disclaimer:
This site does not store any files on its server. We only index and link to content provided by other sites. Please contact the content providers to delete copyright contents if any and email us, we'll remove relevant links or contents immediately.